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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Joyner, J.W. Zarkesh-Ha, P. Davis, J.A. Meindl, J.D. |
| Copyright Year | 2000 |
| Description | Author affiliation: Georgia Inst. of Technol., Atlanta, GA, USA (Joyner, J.W.) |
| Abstract | A complete wire-length distribution for future three-dimensional, homogeneous gigascale integrated (GSI) architectures with variable vertical separation of strata is derived. Because stratal pitch was not found to impact the wire-length distribution significantly, bonded three-dimensional implementations which are technologically feasible can be used to obtain large increases in global clock frequencies. The longest interconnect can be reduced by 30% through the introduction of a single additional stratum. A 93% reduction in the length of the longest interconnect can be obtained through the optimal use of a three-dimensional architecture for a 100 nm ASIC, potentially leading to a 15.8 times increase in global clock frequency. |
| Starting Page | 126 |
| Ending Page | 128 |
| File Size | 373198 |
| Page Count | 3 |
| File Format | |
| ISBN | 0780363272 |
| DOI | 10.1109/IITC.2000.854301 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-06-07 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Stochastic processes Clocks Frequency Wiring Joining processes Transistors Contracts Bonding Application specific integrated circuits Productivity |
| Content Type | Text |
| Resource Type | Article |
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