NDLI: Al deposition temperature process window for 0.20 /spl mu/m Al RIE interconnections

Content Provider	IEEE Xplore Digital Library
Author	Clevenger, L.A. Honda, M. Ravikumar, R. Stojakovic, G.
Copyright Year	1999
Description	Author affiliation: DRAM Dev. Alliance, IBM Microelectron., Hopewell Junction, NY, USA (Clevenger, L.A.)
Abstract	As VLSI dimensions decrease to below 0.2 /spl mu/m, BEOL processing requirements are becoming more stringent. Al conductor line widths and pitches are becoming smaller and aspect ratios are increasing in order to meet design requirements. At the same time, process windows for producing these BEOL wires are becoming more difficult to maintain. This paper focuses on the process window for Al(Cu) deposition temperature for a 0.2 /spl mu/m wide, 0.44 /spl mu/m pitch, Al RIE interconnection used in a 256 Mbit DRAM. While surface roughness and Al texture degrade slightly with increasing deposition temperature, other properties like RIE etchability, /spl Theta/-Al/sub 2/Cu participate distribution and texture, sheet resistance and opens/shorts yield either improve or are unaffected as the Al deposition temperature is increased. All of these parameters combine to suggest a wide process window for Al deposition temperature for 0.2 /spl mu/m Al RIE interconnections.
Starting Page	29
Ending Page	31
File Size	383555
Page Count	3
File Format	PDF
ISBN	0780351746
DOI	10.1109/IITC.1999.787068
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Surface resistance Temperature distribution Very large scale integration Conductors Wires Random access memory Rough surfaces Surface roughness Surface texture Degradation
Content Type	Text
Resource Type	Article

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