NDLI: Semiconductor equipment requirements for Ge and III-V CMOS

Content Provider	IEEE Xplore Digital Library
Author	Ahmed, Khaled
Copyright Year	2012
Description	Author affiliation: Strategic Marketing and Business Development Intermolecular, Inc., San Jose, California, USA (Ahmed, Khaled)
Abstract	Summary form only given. Continued miniaturization of silicon CMOS technology, has resulted in an unprecedented increase in performance of modern-day microprocessors. However, the exponentially rising transistor count has also increased the overall power consumption, making performance per watt of energy consumption as the key figure-of-merit for today's performance microprocessors. Aggressive supply voltage scaling while maintaining the transistor performance is a direct approach to reducing the power dissipation since it reduces the dynamic power quadratically and leakage power linearly. To that effect, narrow gap semiconductor-based (e.g. SiGe, Ge and InGaAs) materials could enable the next generation of logic transistors operating below 0.5 V supply voltages since these materials have excellent transport properties, thereby resulting in high-speed switching under low operating electric fields. However, change of transistor channel and/or source/drain materials will demand new equipment technologies for making different components of the transistor: Gate Stack, Source/Drain, Channel, and contact. In this talk, challenges and opportunities associated with the introduction of Ge and III-V materials will be discussed.
Sponsorship	IEEE Electron Devices Soc.
Starting Page	27
Ending Page	27
File Size	83203
Page Count	1
File Format	PDF
ISBN	9781467327497
ISSN	19308841
e-ISBN	9781467327527
DOI	10.1109/IIRW.2012.6468909
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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