NDLI: Data compression using mixed cascade of nonlinear logic

Content Provider	IEEE Xplore Digital Library
Author	Das, S.R. Shaw, D.L. Biswas, S.N. Assaf, M.H. Morton, S. Ozkarahan, I. Petriu, E.M. Groza, V.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci., Troy Univ., Montgomery, AL, USA (Das, S.R.; Shaw, D.L.; Morton, S.; Ozkarahan, I.) \|\| Sch. of Eng. & Comput. Sci., Indep. Univ., Dhaka, Bangladesh (Biswas, S.N.) \|\| Sch. of Inf. Technol. & Eng., Univ. of Ottawa, Ottawa, ON, Canada (Petriu, E.M.; Groza, V.) \|\| Dept. of Electr. & Electron. Eng., Univ. of the South Pacific, Suva, Fiji (Assaf, M.H.)
Abstract	The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zeroaliasing (aliasing-free) space compression hardware for single stuck-line faults, extending well-known concept of conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test (CUT), the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other pair of response data outputs being simultaneously fault detection compatible) with respect to two-input AND/NAND and/or OR/NOR logic. The process is illustrated with the design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM and COMPACTEST, though, because of space constraints, only some partial results on simulation on ISCAS 89 full-scan sequential benchmark circuits using ATALANTA are provided here.
Sponsorship	IEEE Instrum. Meas. Soc.
Starting Page	1544
Ending Page	1549
File Size	232000
Page Count	6
File Format	PDF
ISBN	9781467346214
ISSN	10915281
e-ISBN	9781467346238
DOI	10.1109/I2MTC.2013.6555673
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Compaction Logic gates Built-in self-test Benchmark testing Integrated circuit modeling fault detection and conditional fault detection compatibility Aliasing-free (zero-aliasing) space compaction ATALANTA built-in self-testing in very large scale integration circuits and systems
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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