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  1. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems.
  2. 2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
  3. Introspection-Based Fault Tolerance for COTS-Based High-Capability Computation in Space
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2008 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
Table of contents
Message from the Editors
Reviewing Committee
The Shape of Things to Come: Future Potential of "Heavy Node" Multi-Core HPC Architectures
Effect of Reordering Internal Messages in MPI Broadcast According to the Load Imbalance
Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network
Unified Programming Environment for Heterogeneous Distributed Parallel Systems
A PLD Architecture for High Performance Computing
Automatic Application of Last-Touch Instructions for Leakage Energy Reduction
Design and Power Performance Evaluation of On-Chip Memory Processor with Arithmetic Accelerators
Register File Reliability Analysis Through Cycle-Accurate Thermal Emulation
Low-Power and High-Performance Communication Mechanism for Dependable Embedded Systems
Introspection-Based Fault Tolerance for COTS-Based High-Capability Computation in Space
Author index
Innovative architecture for future generation high-performance processors and systems (iwia 2007)
International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'06)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'05)
Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'04)
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
2001 Innovative Architecture for Future Generation High-Performance Processors and Systems
Innovative Architecture for Future Generation High-Performance Processors and Systems (Cat. No.PR00650)
Innovative Architecture for Future Generation High-Performance Processors and Systems
Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems

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Introspection-Based Fault Tolerance for COTS-Based High-Capability Computation in Space

Content Provider IEEE Xplore Digital Library
Author James, M.L. Shapiro, A.A. Springer, P.L. Zima, H.P.
Copyright Year 2008
Description Author affiliation: Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA (James, M.L.; Shapiro, A.A.; Springer, P.L.; Zima, H.P.)
Abstract Future missions of deep space exploration face the challenge of designing, building,and operating progressively more capable autonomous spacecraft and planetary rovers. Given the communication latencies and bandwidth limitations for such missions, the need for increased autonomy becomes mandatory, along with the requirement for enhanced on-board computational capabilities while in deep space or time-critical situations. This will result in dramatic changes in the way missions will be conducted and supported by on-board computing systems. Specifically, the traditional approach of relying exclusively on radiation-hardened hardware and modular redundancy will not be able to deliver the required computational power. As a consequence, such systems are expected to include high-capability low-power components based on emerging Commercial-Off-The-Shelf (COTS) multi-core technology. This paper describes the design of a generic framework for introspection that supports runtime monitoring and analysis of program execution as well as a feedback-oriented recovery from faults. One of the first applications of this framework will be to provide flexible software fault tolerance matched to the requirements and properties of applications by exploiting knowledge that is either contained in an application knowledge base, provided by users, or automatically derived from specifications. A prototype implementation is currently in progress at the Jet Propulsion Laboratory, California Institute of Technology, targeting a cluster of Cell Broadband Engines.
Starting Page 74
Ending Page 83
File Size 180074
Page Count 10
File Format PDF
ISBN 9781424464654
ISSN 15373223
e-ISBN 9781424464661
DOI 10.1109/IWIA.2008.11
Language English
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date 2008-01-21
Publisher Place USA
Access Restriction Subscribed
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword Fault tolerance Application software Space exploration Space vehicles Delay Bandwidth Space missions Time factors Hardware Redundancy introspection space-borne computing high-performance computing fault tolerance
Content Type Text
Resource Type Article
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