NDLI: A PLD Architecture for High Performance Computing

Content Provider	IEEE Xplore Digital Library
Author	Hirakawa, N. Yoshihara, M. Tanigawa, K. Hironaka, T. Sato, M.
Copyright Year	2008
Description	Author affiliation: Graduated Sch. of Eng., Tokyo Metropolitan Univ., Tokyo, Japan (Sato, M.) \|\| Graduated Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan (Hirakawa, N.; Yoshihara, M.; Tanigawa, K.; Hironaka, T.)
Abstract	In recent years, Field Programmable Gate Arrays (FPGAs) have been used for High Performance Computing (HPC). Because there is a significantly difference between configuration speed of FPGA and execution speed of Central Processing Unit (CPU), the difference causes performance degradation. To resolve of this problem, we proposed MPLD as a new Programmable Logic Device (PLD) architecture with high speed reconfiguration. The merits of the MPLD in HPC are high speed configuration and easy partial configuration.This is achieved by the configuration method which is same as write memory access of conventional parallel memory. In this paper, we describe the problems of FPGA on using it in HPC, and present the MPLD architecture which solves the problems. Some evaluation results of the prototype MPLD chip which implemented by using five metal layers ROHM 0.18¿m CMOS technology are also presented. As results, memory capacity of the prototype MPLD was 49152bit, and the core area was 1767.54 × 1690.96¿m2 and the number of metal layers used for wiring was three. The achieved configuration time is about 6.6¿sec for whole prototype MPLD. The configuration speed of the prototype MPLD is about 11.7 times higher than AS configuration used for Altera FPGAs.
Starting Page	35
Ending Page	42
File Size	432120
Page Count	8
File Format	PDF
ISBN	9781424464654
ISSN	15373223
e-ISBN	9781424464661
DOI	10.1109/IWIA.2008.12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture High performance computing Field programmable gate arrays Prototypes Central Processing Unit CMOS technology Programmable logic arrays Degradation Programmable logic devices Wiring easy partial configuration PLD FPGA MPLD high speed configuration
Content Type	Text
Resource Type	Article

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