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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mamani, H. Saeedi, H. Eslami, A. Pishro-Nik, H. |
| Copyright Year | 2012 |
| Description | Author affiliation: Department of Electrical and Computer Engineering, Tarbiat Modares University, Tehran, Iran (Mamani, H.; Saeedi, H.) || Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA (Eslami, A.; Pishro-Nik, H.) |
| Abstract | Generalized Extrinsic Information Transfer (GEXIT) charts were introduced as an extension of EXIT charts which have an extensive use in analysis and design of many iterative schemes including Low-Density Parity-Check (LDPC) codes. While a powerful as well as an insightful concept, their full potential as a designing tool for LDPC code ensembles has not been realized due to some missing steps. This papers aims at filling these gaps by proving some important properties of GEXIT charts and using them to design capacity-approaching LDPC code ensembles. The primary results on GEXIT charts are limited to regular variable and check node degrees. Moreover, variable node GEXIT curves have only been derived for the case where no physical channel is present. In a recent paper, GEXIT curves for irregular variable node and check node degree distributions have been derived. In this paper, we derive GEXIT charts of LDPC code ensembles over binary-input output-symmetric memoryless channels with any channel parameter. For the case of binary symmetric channel, we derive closed form expression for the GEXIT curve of variable nodes. We also propose to use an alternative representation of GEXIT charts in which we plot the inverse of variable node GEXIT curve together with dual GEXIT curve of the check node. We prove that the area theorem still holds in this case. Using these results, we analyze and design capacity-approaching LDPC codes using GEXIT charts. |
| Starting Page | 2336 |
| Ending Page | 2340 |
| File Size | 154927 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781467325806 |
| ISSN | 21578117 |
| e-ISBN | 9781467325790 |
| e-ISBN | 9781467325783 |
| DOI | 10.1109/ISIT.2012.6283930 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-07-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parity check codes Equations Mathematical model Memoryless systems Computers Educational institutions |
| Content Type | Text |
| Resource Type | Article |
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