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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xiaolin Wang Yan Cai Sheng Xiao Weibo Gong |
| Copyright Year | 2008 |
| Description | Author affiliation: Analog Devices Inc., Wilmington, MA (Xiaolin Wang) |
| Abstract | Recently there has been a great deal of interest in load-balancing switches due to their simple architecture and high bandwidth. In this paper we propose a three-stage load- balancing switch along with output load-balancing to address the mis-sequencing problem. We show that our proposed scheme provides a delay guarantee bounded by the delay of an OQ switch with the same input traffic plus a constant while achieving 100% throughput for admissible traffic with (sigma, rho) -upper constraint. |
| Starting Page | 1993 |
| Ending Page | 2001 |
| File Size | 215073 |
| Page Count | 9 |
| File Format | |
| ISBN | 9781424420254 |
| ISSN | 0743166X |
| DOI | 10.1109/INFOCOM.2008.264 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-04-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fabrics Optical switches Packet switching Delay Bandwidth Throughput Traffic control Field-flow fractionation Scheduling algorithm Communications Society |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Science Electrical and Electronic Engineering |
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