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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kumar, S. Turner, J. Crowley, P. |
| Copyright Year | 2008 |
| Description | Author affiliation: Comput. Sci. & Eng., Washington Univ., St. Louis, MO (Kumar, S.; Turner, J.; Crowley, P.) |
| Abstract | Hash tables are extensively used in networking to implement data-structures that associate a set of keys to a set of values, as they provide O(1), query, insert and delete operations. However, at moderate or high loads collisions are quite frequent which not only increases the access time, but also induces non- determinism in the performance. Due to this non-determinism, the performance of these hash tables degrades sharply in the multi-threaded network processor based environments, where a collection of threads perform the hashing operations in a loosely synchronized manner. In such systems, it is critical to keep the hash operations more deterministic. A recent series of papers have been proposed, which employs a compact on-chip memory to enable deterministic and fast hash queries. While effective, these schemes require substantial on- chip memory, roughly 10-bits for every entry in the hash table. This limits their general usability; specifically in the network processor context, where on-chip resources are scarce. In this paper, we propose a novel hash table construction called Peacock hash, which reduces the on-chip memory by more than 10-folds while keeping a high degree of determinism in performance. This significantly reduced on-chip memory not only makes Peacock hashing much more appealing for the general use but also makes it an attractive choice for the implementation of a hash hardware accelerator on a network processor. |
| Starting Page | 101 |
| Ending Page | 105 |
| File Size | 349902 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424420254 |
| ISSN | 0743166X |
| DOI | 10.1109/INFOCOM.2008.29 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-04-13 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Yarn Network-on-a-chip Filters Degradation Costs System performance Communications Society Computer science Data engineering Usability |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Science Electrical and Electronic Engineering |
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