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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ruano, O. Maestro, J.A. Reviriego, P. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. Ing. Inf., Univ. Antonio de Nebrija, Madrid (Ruano, O.; Maestro, J.A.; Reviriego, P.) |
| Abstract | In this paper, we study and present two techniques to improve the performance of a simulation-based fault injection platform that inserts bit flips in order to model soft errors on digital circuits. The platform is based on the ESA Data Systems Divisionpsilas SEE simulation tool. In contrast with methods based on emulation, the proposed approach reduces the complexity and costs, supplying a test environment with the same reliability as emulation systems. Only one disadvantage appears when comparing both methodologies: the lower performance of the simulation in cases where the fault injection campaigns are very large. Two proposals have been developed in order to address this drawback: the first one is based on software (through checkpoints) and the second one uses parallel computation. |
| Starting Page | 2299 |
| Ending Page | 2304 |
| File Size | 216832 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424416653 |
| DOI | 10.1109/ISIE.2008.4676995 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-06-30 |
| Publisher Place | UK |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Performance analysis Analytical models Circuit simulation Circuit faults Emulation Digital circuits Data systems Costs Circuit testing System testing |
| Content Type | Text |
| Resource Type | Article |
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