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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Graefe, V. Fleder, K. |
| Copyright Year | 1991 |
| Description | Author affiliation: Inst. fuer Messtech., Univ. der Bundeswehr Munchen, Neubiberg, Germany (Graefe, V.; Fleder, K.) |
| Abstract | Concepts, implementation, and evaluation of a novel processor for feature extraction are described. The processor is a freely programmable RISC (reduced instruction set computer) machine with a modified Harvard architecture, designed to operate as a coprocessor in combination with each parallel processor of the multiprocessor robot vision system BVV 3. It performs 10/sup 7/ complex operations per second, each of which may comprise up to seven elementary operations. The processor has been tested in a number of real-world experiments, including road following. In this application it has demonstrated its ability to analyze a TV image in less than 4 ms. The analysis included six independent tracking processes on different parts of the road's edges, six spatial line-following processes attached to the trackers, and two geometrical models for both edges of the road. |
| Starting Page | 2019 |
| Ending Page | 2024 |
| File Size | 550867 |
| Page Count | 6 |
| File Format | |
| ISBN | 0879426888 |
| DOI | 10.1109/IECON.1991.239031 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-10-28 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Coprocessors Feature extraction Roads Reduced instruction set computing Computer aided instruction Computer vision Concurrent computing Computer architecture Robot vision systems Testing |
| Content Type | Text |
| Resource Type | Article |
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