NDLI: A comparative analysis of different fault simulation techniques for VLSI circuits testing

Content Provider	IEEE Xplore Digital Library
Author	Torroja, Y. Riesgo, T. de la Torre, E. Uceda, J.
Copyright Year	1991
Description	Author affiliation: ETSII Div. de Ingenieria Electron., Univ. Politecnica de Madrid, Spain (Torroja, Y.; Riesgo, T.; de la Torre, E.; Uceda, J.)
Abstract	Two solutions for the problem of fault simulation of digital integrated circuits and a comparison of their performance are presented. The first fault simulator is a serial simulator. Because of the efficiency of the logic simulation algorithm the results are quite good. The second is a differential fault simulator which takes advantage of the order in which the faults are simulated. These fault simulators will work in an automatic test pattern generation (ATPG) system which deals with combinatorial or sequential scan designed circuits considering the stuck-at-0, 1 fault model. An overview of ATPG systems and different methodologies used in fault simulation is also presented. In the description of the suggested approach, special emphasis is given to the basic logic simulator used to implement the fault simulators. Benchmarks have been developed on ISCAS circuits and were obtained in terms of CPU time, fault coverage and number of events, for a set of random vectors.
Starting Page	1226
Ending Page	1231
File Size	536818
Page Count	6
File Format	PDF
ISBN	0879426888
DOI	10.1109/IECON.1991.239266
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-10-28
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Analytical models Circuit simulation Very large scale integration Circuit testing Automatic test pattern generation Sequential analysis Logic Software tools Costs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

System level test generation and fault simulation for VLSI circuits

Identifying redundancies using reduced symbolic simulation [digital VLSI circuits]

CRIS: A test cultivation program for sequential VLSI circuits

Fault distinguishing pattern generation

Fault-based automatic test generator for linear analog circuits

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits

A method to reduce power dissipation during test for sequential circuits

Handling faults in a VLSI CAD environment

Hierarchical fault simulation in combinational circuits

A comparative analysis of different fault simulation techniques for VLSI circuits testing

Similar Documents

System level test generation and fault simulation for VLSI circuits

Identifying redundancies using reduced symbolic simulation [digital VLSI circuits]

CRIS: A test cultivation program for sequential VLSI circuits

Fault distinguishing pattern generation

Fault-based automatic test generator for linear analog circuits

Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits

A method to reduce power dissipation during test for sequential circuits

Handling faults in a VLSI CAD environment

Hierarchical fault simulation in combinational circuits

A comparative analysis of different fault simulation techniques for VLSI circuits testing