NDLI: Redundant states in test control block design

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Proceedings ETC 93 Third European Test Conference

Fast, accurate, integrated gate and switch-level fault simulation

Optimized test cost using fault probabilities

Fault coverage and yield predictions: do we need more than 100% coverage?

Trade-offs in scan path and BIST implementations for RAMs

Is there any future for deterministic self-test of embedded RAMs?

Random test length for bounded faults in RAMs

Functional memory array testing using associative search algorithms

A contribution to testing of analog integrated circuits in the DC domain

On the application of fault detection observers to analog circuit testing

A fault signature approach to analog devices testing

Analog fault diagnosis: a fault clustering approach

Partial scan: what problem does it solve?

Fast test pattern generation for all path delay faults considering various test classes

A reconvergent fanout analysis for the CPT algorithm used in delay-fault diagnosis

Concurrent error detection of CMOS digital and analog faults

Implementation of the transient response measurement of mixed-signal circuits

Towards a mixed-signal testability bus standard P1149.4

System-level fault modeling and test pattern generation with process algebras

A fuzzy decision-making approach for test space exploration

Testability and test protocol expansion in hierarchical macro testing

Reliability aspects of defect analysis

A framework for test quality assessment

The effect of guardbands on errors in production testing

Proceedings of ETC 93. Third European Test Conference (Cat. No.93TH0494-5)

On scan path design for stuck-open and delay fault detection

Redundant states in test control block design

On the testability of FFT arrays

Test pattern generation for multiple stuck-at faults

Algebraic ATPG of combinational circuits using binary decision diagrams

Combinational ATPG theorems for identifying untestable faults in sequential circuits

I-path analysis

Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits

Essential testability guidelines for current technology

A deductive method for simulating transistor stuck-open faults in CMOS circuits

Fault simulation for synchronous sequential circuits under the multiple observation time testing approach

Multiple-domain concurrent and comparative simulation

Phase coherent, event synchronized test system architecture

Modules for gigahertz digital testing of ECL

Analog test signal generation on a digital tester

Checking signatures on boundary scan boards

Basic boundary-scan for in-circuit test

Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals

Implementing BIST and boundary-scan in a digital signal processor ASIC for radiocommunication applications

Incoming inspection of FPGA's

Absolute dynamic measurements of temperature changes in electronic components from a thermoreflectance optical test probe

Testing mixed signal ASICs through the use of supply current monitoring

Current vs. logic testability of bridges in scan chains

Influence of IC synthesis on the random pattern testability of parametric bridging faults

Experience with biased random pattern generation to meet the demand for a high quality BIST

A pattern skipping method for weighted random pattern testing

Fast and high quality in-circuit test development through expert debug

Using EDIF in IC testing: experience from the Everest project

MixTest: a mixed signal extension to the HP82000

Aliasing minimization in signature analysis testing

Modular-addition signature analysis for built-in self-test

Experimental results on aliasing errors in circular BIST design

Interconnect testing for bus-structured systems

Testing interconnects: a pin adjacency approach

A new DFT technique to reduce test duration for sequential circuits

RT level test scheduling

A new and secure selftest scheme for block cipher implementations

Methodology of detection of spurious signals in VLSI circuits

An approach to mixed circuits testing

Testing of analogue to digital converter macros in ASICs

Defect level as a function of fault coverage and yield

Functional validation methods for VLSI-based systems

Resynthesis for testability of redundant combinational circuits

The structure of complete test sets for programmable logic arrays

A model for functional test generation and testability analysis

On the diagnosability of DNMR testing

A high-level test program language for analog and mixed-signal test program development

Automated comparison of measured versus expected signals in mixed signal device testing and its effect on fault localization strategies

Design for testability techniques applicable to analog circuits

Testing analog circuits by using a sigma-delta modulator

FNSIM: a functional fault simulator for efficient testability analysis

Mixed-signal automatic test program generation

Testing of resistive bridging faults in CMOS flip-flop

New methods for parallel pattern fast fault simulation for synchronous sequential circuits

On automatic fault isolation using DFT methodology for active analog filters

Analysis of voltage forcing consequences during in-circuit testing

Logic circuit extraction for bridging fault equivalence identification in CMOS ICs

Testing crossbar switch interconnection networks

Modelling delay in symbolic test for data paths with partial scan

Functional level testability analysis for digital circuits

[1989] Proceedings of the 1st European Test Conference

Redundant states in test control block design

Content Provider	IEEE Xplore Digital Library
Author	Thijssen, L. Bouwman, F. Vink, H.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands (Thijssen, L.)
Abstract	The number of states in sequential circuit designs does not usually equal to 2/sup n/ This results in a number of redundant state codes. It has been accepted that redundant state codes are used as don't cares in the next-state equations. The target is a reduction of the hardware costs. In doing so the behaviour of the circuit in redundant states has not been specified in advance. Error handling and testability may be a serious problem. This paper shows there is an alternative. Redundant states can be fully specified in a simple and meaningful way, often with even better hardware efficiency than a state assignment with don't cares. Some additional results in encoding test control blocks are also given.<>
Starting Page	211
Ending Page	218
File Size	547215
Page Count	8
File Format	PDF
ISBN	0818633603
DOI	10.1109/ETC.1993.246554
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-04-19
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Clocks Equations Hardware Logic testing Digital circuits History Shift registers Sequential circuits Costs
Content Type	Text
Resource Type	Article

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