NDLI: An economical scan design for sequential logic test generation

Content Provider	IEEE Xplore Digital Library
Author	Cheng, K.-T. Agrawal, V.D.
Copyright Year	1989
Description	Author affiliation: AT&T Bell Lab., Murray Hill, NJ, USA (Cheng, K.-T.; Agrawal, V.D.)
Abstract	A method of partial scan design in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit is presented. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles to reduce sequential depth. Tests for the resulting circuit can be efficiently generated by a sequential logic test generator. An independent control of the scan clock allows the insertion of scan sequences within the vector sequence produced by the test generator. Experimental results on a 5000 gate circuit show that a test coverage above 98% could be obtained by scanning just 5% of the flip-flops. In addition, the authors give the design of a scan flip-flop to reduce the input pin and signal routing overheads in a single-clock design.<>
Starting Page	28
Ending Page	35
File Size	568905
Page Count	8
File Format	PDF
ISBN	0818619597
DOI	10.1109/FTCS.1989.105539
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-06-21
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Circuit testing Sequential analysis Flip-flops Clocks Circuit faults Signal design Automatic control Sequential circuits Routing
Content Type	Text
Resource Type	Article

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