NDLI: Massively parallel computing system for research and development applications

Content Provider	IEEE Xplore Digital Library
Author	Johnson, W.K.
Copyright Year	1988
Description	Author affiliation: Amber Eng. Inc., Goleta, CA, USA (Johnson, W.K.)
Abstract	A description of a SIMD (single-instruction multiple-data) processor development system (SPDS) is presented. The SPDS is designed to provide a cost-effective, turn-key solution to users desiring to explore massively parallel computing applications. The SPDS, which is based upon the geometric-arithmetic parallel processor (GAPP) integrated circuit, contains a two-dimensional array of between 2304 and 10368 processing elements. This processing element array operates in a classical single-instruction/multiple-data fashion. The SPDS processing electronics can be connected to any AT-bus-compatible computer via an interface card. The SPDS works in conjunction with an optional frame grabber card to acquire RS-170 imagery and to display processed results on a standard analog monitor. Software bundled with the SPDS runs under the MS-DOS operating system and includes a compiler/linker/microcode generator for the GAPP array, a GAPP utility library in source code form, and a menu-driven user interface with interactive symbolic debugging capability.<>
Starting Page	407
Ending Page	411
File Size	313012
Page Count	5
File Format	PDF
ISBN	0818658924
DOI	10.1109/FMPC.1988.47461
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-10-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Research and development Application software Computer interfaces Computer displays Computerized monitoring Software debugging Operating systems Software libraries User interfaces
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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