NDLI: Implementation of a volume rendering on coarse-grained reconfigurable multiprocessor

Content Provider	IEEE Xplore Digital Library
Author	Seunghun Jin Sangheon Lee Moo-Kyoung Chung Yeongon Cho Soojung Ryu
Copyright Year	2012
Description	Author affiliation: Samsung Advanced Institute of Technology, MT. 14-1, Nongseo-dong, Giheung-gu, Yongin-si Gyeonggi-do, 446-712 South Korea (Seunghun Jin; Sangheon Lee; Moo-Kyoung Chung; Yeongon Cho; Soojung Ryu)
Abstract	In this paper, we present reconfigurable multiprocessor architecture for volume rendering. The multiprocessor consists of sixteen reconfigurable processors to exploit data parallelism of the volume rendering. Each processor has VLIW core and reconfigurable coarse-grained array specialized for control and data-intensive part of the program, respectively. The coarse-grained array can be configured dynamically, so that it can efficiently process different kernels of the volume rendering. The multiprocessor is implemented using verilog HDL and realized onto a commercial FPGA-based prototyping system. The experimental result shows that the presented multiprocessor has comparable performance to high-end desktop GPUs.
Starting Page	243
Ending Page	246
File Size	3884060
Page Count	4
File Format	PDF
ISBN	9781467328463
e-ISBN	9781467328456
e-ISBN	9781467328449
DOI	10.1109/FPT.2012.6412142
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-10
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Rendering (computer graphics) Program processors Computer architecture Casting Parallel processing VLIW Kernel
Content Type	Text
Resource Type	Article

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