NDLI: FPGA design productivity a discussion of the state of the art and a research agenda

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2008 International Conference on Field-Programmable Technology

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Technical Program Committee

Re-visiting the challenges of programmable concurrent architectures

FPGA timing, power, signal integrity and other challenges at 65 and 45 nm

FPGA design productivity a discussion of the state of the art and a research agenda

Co-optimisation of datapath and memory in outer loop pipelining

Wave-pipelined signaling for on-FPGA communication

Portable and scalable FPGA-based acceleration of a direct linear system solver

A system-level stochastic circuit generator for FPGA architecture evaluation

An FPGA-specific approach to floating-point accumulation and sum-of-products

Optimizing residue arithmetic on FPGAs

Reconfigurable array for transcendental functions calculation

Optimizing coarse-grained units in floating point hybrid FPGA

Hardware acceleration of approximate palindromes searching

PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters

Design and implementation of a high performance financial Monte-Carlo simulation engine on an FPGA supercomputer

Estimation of sample mean and variance for Monte-Carlo simulations

Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain

A transition probability based delay measurement method for arbitrary circuits on FPGAs

A profiler for a heterogeneous multi-core multi-FPGA system

Defining neighborhood relations for fast spatial-temporal partitioning of applications on reconfigurable architectures

Accelerating hardware simulation: Testbench code emulation

Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors

A scalable reconfiguration mechanism for fast dynamic reconfiguration

Memory security management for reconfigurable embedded systems

ACS: An Addressless Configuration Support for efficient partial reconfigurations

An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration

A run-length based connected component algorithm for FPGA implementation

Optimised single pass connected components analysis

Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs

FPGA implementation and analysis of random delay insertion countermeasure against DPA

Netlist-level IP protection by watermarking for LUT-based FPGAs

Modelling and compensating for clock skew variability in FPGAs

Kernel sharing on reconfigurable multiprocessor systems

Evaluating the impact of customized instruction set on coarse grained reconfigurable arrays

Balanced allocation of compute time in hardware-accelerated systems

Processor customization for wearable bio-monitoring platforms

An implementation of a watershed algorithm based on connected components on FPGA

A new flexible PR domain model to replace the fixed multi-PR region model for DPR systems

Exploring hard and soft networks-on-chip for FPGAs

An approach for downscaling images for real-time pattern detection

Dynamically programmable Reed Solomon processor with embedded Galois Field multiplier

Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation

Synthesis of efficiently reconfigurable datapaths for reconfigurable computing

Makespan minimization in automatic synthesis of multiprocessor systems from parallel programs

A new coarse-grained FPGA architecture exploration environment

An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays

An 11,424-gate dynamic optically reconfigurable gate array VLSI

A systolic regular expression pattern matching engine and its application to network intrusion detection

Evaluating power and energy consumption of FPGA-based custom computing machines for scientific floating-point computation

A dynamically reconfigurable Field Programmable Gate Array hardware foundation for security applications

Quad-level bit-stream signal processing on FPGAs

A low power reconfigurable heterogeneous architecture for a mobile SDR system

High level quantitative interconnect estimation for Early Design Space Exploration

Unrolling-based loop mapping and scheduling

Concurrent timing based and routability driven depopulation technique for FPGA packing

Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique

Extending Booth algorithm to multiplications of three numbers on FPGAs

A scalable FPGA architecture for non-linear SVM training

A low memory bandwidth Gaussian mixture model (GMM) processor for 20,000-word real-time speech recognition FPGA system

Creating digital fingerprints on commercial field programmable gate arrays

An area-efficient FPGA realisation of a codebook-based image compression method

A floating-point solver for band structured linear equations

Efficient FPGA elliptic curve cryptographic processor over $GF(2^{m})$

An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs

Delay evaluation of 90nm CMOS multi-context FPGA with shift-register-type temporal communication module for large-scale circuit emulation

ρ-VEX: A reconfigurable and extensible softcore VLIW processor

Automatic generation of decomposition based matrix inversion architectures

Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI

Real-time FPGA architecture of extended linear convolution for digital image scaling

2007 International Conference on Field-Programmable Technology

2006 IEEE International Conference on Field Programmable Technology

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

FPGA design productivity a discussion of the state of the art and a research agenda

Content Provider	IEEE Xplore Digital Library
Author	Nelson, B.
Copyright Year	2008
Abstract	Summary form only given. As configurable computing matures there is continued interest in design productivity. While configurable computing machines (CCMs) are touted as re-usable, re-configurable platforms for accelerated computing, the design processes and tools employed to map applications to such platforms may have more in common with hardware ASIC design tools and processes than with conventional software development tools and processes. To address this there continues to be research in the community on higher-level languages, reusable core libraries, improved CAD tools, debug infrastructure, etc. but little focus on the big picture. That is, how do all these pieces fit together into a comprehensive approach for improving design productivity? Is a 10x increase in design productivity feasible in the next few years? How about 20x? What are the key research problems that must be solved? What are the most promising approaches to solving these problems? My talk will focus on these questions and will draw from the results of two events related to FPGA design productivity which were held recently. First, the day before FPT'2009, a workshop is being held at Taiwan National University to discuss these questions with all FPT attendees invited to participate. Details are found on the FPT conference website. Special guest speakers at the workshop will be asked to provide their viewpoints on FPGA design productivity and components of a research agenda to increase productivity over the next 5-10 year horizon. Second, during the past year in the United States, two multi-university research teams have focused on developing and outlining a research agenda to address FPGA design productivity, culminating in a workshop held in Salt Lake City during June 2008. My talk will discuss the current challenges in FPGA design productivity and address a range of solutions, based in part on the results of the above two workshops as well as other efforts going on in the research community.
File Size	90649
File Format	PDF
ISBN	9781424437832
DOI	10.1109/FPT.2008.4762358
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-08
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Productivity Process design Acceleration Application software Hardware Application specific integrated circuits Programming Software libraries Design automation
Content Type	Text
Resource Type	Article

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