NDLI: Improving Bounds for FPGA Logic Minimization

Content Provider	IEEE Xplore Digital Library
Author	Todman, T. Haofan Fu Mencer, O. Luk, W.
Copyright Year	2007
Description	Author affiliation: Imperial Coll. London, London (Todman, T.; Haofan Fu; Mencer, O.; Luk, W.)
Abstract	We present a methodology for improving the bounds of combinational designs implemented on networks of lookup tables, moving them closer to the theoretical minimum. Our work effectively extends optimality to span logic minimization and technology mapping. We obtain a proof of optimality by restricting ourselves to 4-input look-up tables (LUTs) and generating all possible circuits up to a certain area or latency depending on the optimization mode. Since simple-minded generation would take a long time, we develop levels of abstraction (steps) and techniques to restrict and order the search space, and produce results in practical time. We use logic decomposition to break up large designs, using the resulting trees to guide our search and prune the search space. The price of this optimality is that we are limited to small blocks; however, such blocks can be used to build larger designs.
Starting Page	245
Ending Page	248
File Size	2152348
Page Count	4
File Format	PDF
ISBN	9781424414710
DOI	10.1109/FPT.2007.4439257
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Minimization Table lookup Upper bound Space technology Logic circuits Logic design Educational institutions Design optimization Delay
Content Type	Text
Resource Type	Article

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