NDLI: Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation

Content Provider	IEEE Xplore Digital Library
Author	Lee, D. Cheung, R.C.C. Villasenor, J.D. Luk, W.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA (Lee, D.)
Abstract	We present the design and implementation of a Gaussian random number generator (GRNG) via hierarchical segmentation. Gaussian samples are generated using the inversion method, which involves the evaluation of the inverse Gaussian cumulative distribution function (IGCDF). The IGCDF is highly nonlinear and is evaluated via piecewise polynomial approximations (splines) with a hierarchical segmentation scheme that involves uniform splines and splines with size varying by powers of two. This segmentation approach adapts the spline sizes according to the non-linearity of the function, allowing efficient evaluation of the IGCDF. Bit-widths of the fixed-point polynomial coefficients and arithmetic operators are optimized in an analytical manner to guarantee a precision accurate to one unit in the last place. Our architecture generates 16-bit Gaussian samples accurate to 8.2cr (standard deviations). A pipelined implementation on a Xilinx Virtex-4 XC4LX100-12 FPGA yields 371 MHz and occupies 543 slices, 2 block RAMs, and 2 DSP slices, generating one sample every clock cycle
Starting Page	33
Ending Page	40
File Size	360499
Page Count	8
File Format	PDF
ISBN	0780397282
DOI	10.1109/FPT.2006.270388
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-13
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Random number generation Distribution functions Polynomials Application software Table lookup Educational institutions Fixed-point arithmetic Field programmable gate arrays Digital signal processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Composite Look-Up Table Gaussian Pseudo-Random Number Generator

Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform

Using FPGA resources for direct generation of multivariate Gaussian random numbers

High quality uniform random number generation through LUT optimised linear recurrences

Table-based polynomials for fast hardware function evaluation

An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers

Automated fixed-point precision optimization

FPGA Gaussian random number generator based on quintic hermite interpolation inversion

Efficient Large Integer Squarers on FPGA

Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation

Similar Documents

Composite Look-Up Table Gaussian Pseudo-Random Number Generator

Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform

Using FPGA resources for direct generation of multivariate Gaussian random numbers

High quality uniform random number generation through LUT optimised linear recurrences

Table-based polynomials for fast hardware function evaluation

An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers

Automated fixed-point precision optimization

FPGA Gaussian random number generator based on quintic hermite interpolation inversion

Efficient Large Integer Squarers on FPGA

Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation