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2015 International Conference on Field Programmable Technology (FPT)

2013 International Conference on Field-Programmable Technology (FPT)

2012 International Conference on Field-Programmable Technology

2011 International Conference on Field-Programmable Technology

2010 International Conference on Field-Programmable Technology

2009 International Conference on Field-Programmable Technology

2008 International Conference on Field-Programmable Technology

2007 International Conference on Field-Programmable Technology

2006 IEEE International Conference on Field Programmable Technology

2006 IEEE International Conference on Field Programmable Technology (FPT2006)

[CD Front Cover]

[CD Back Cover]

CDROM FTP 2006 Session List

FPT 2006 Table of contents [CDROM TOC]

FPT 2006 brief author index [CDROM]

FPT 2006 detailed author index [CDROM]

FPT 2006 The End of Indexes [CDROM]

Proceedings 2006 IEEE International Conference on Field Programmable Technology

Message from the General Chair

Message from the Technical Program Chairs

Technical Program Committee

Additional reviewers

Invited Keynote 1: Closing the gap between FPGAs and ASICs

Invited Keynote 2: Applications of programmable logic in modern particle physics experiments

Table of contents

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Author Index [Book]

Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters

Granularity aspects for the design of multi-level reconfigurable architectures

Evaluation of granularity on threshold voltage control in flex power FPGA

Robust and real-time automatic target recognition using partial hausdorff distance measure on reconfigurable hardware

Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation

Seed-based genomic sequence comparison using a FPGA/FLASH accelerator

An FPGA implementation of the simplex algorithm

On-line scheduling of real-time tasks for reconfigurable computing system

Efficient algorithm for functional scheduling in hardware/software co-design

Generating hardware from OpenMP programs

Reconfigurable FLUX networks

Interconnect driver design for long wires in field-programmable gate arrays

Within-die delay variability in 90nm FPGAs and beyond

A highly parameterizable parallel processor array architecture

Optimizing the critical loop in the H.264/AVC CABAC decoder

Regular expression matching for reconfigurable packet inspection

Automated design space exploration of FPGA-based FFT architectures based on area and power estimation

Sigma-delta based clock recovery using on-chip PLL in FPGA

A hardware cache memcpy accelerator

A novel memory architecture for elliptic curve cryptography with parallel modular multipliers

Memory support design for LU decomposition on the starbridge hyper-computer

FPGA-based MSB-first bit-serial variable block size motion estimation processor

FPGA accelerated tate pairing based cryptosystems over binary fields

A comparison of 2-D discrete wavelet transform computation schedules on FPGAs

Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route

Multithreaded virtual-memory-enabled reconfigurable hardware accelerators

FPGA core watermarking based on power signature analysis

FPGA acceleration of the tate pairing in characteristic 2

FADES: a fault emulation tool for fast dependability assessment

An adaptive frequency control method using thermal feedback for reconfigurable hardware applications

FPGA implementation of a fuzzy controller for automobile DC-DC converters

An adaptive and predictive architecture for parameterised PIV algorithms

A real time programmable encoder for low density parity check code targeting a reconfigurable instruction cell architecture

Summarizing a time-sensitive control-flow checking monitoring for multitask systems-on-chip

Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs

Implementation of a real-time multiple input multiple output channel estimator on the smart antenna software radio test system platform using the Xilinx Virtex 2 Pro Field Programmable Gate Array

Efficient management of custom instructions for run-time reconfigurable instruction set processors

FPGA implementation for an iris biometric processor

FPGA implementation of tabu search for the quadratic assignment problem

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration

Hardware join Java: a unified hardware/software language for dynamic partial runtime reconfigurable computing applications

An FPGA based generic prototyping platform employed in a CMOS laser Doppler blood flow camera

An adaptive Viterbi decoder on the dynamically reconfigurable processor

PowerBit - power aware arithmetic bit-width optimization

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology

Hardware channel model for ultra wideband systems

A leakage aware design methodology for power-gated programmable architectures

A C compiler for implementing FPGA based bit-serial DSP systems

Performance evaluations of ReconfigME

Power estimation of a LUT-based MPGA

An FPGA-based floating-point processor array supporting a high-precision dot product

Communications infrastructure generation for modular FPGA reconfiguration

Fuzzy modular multiplication architecture and low complexity IPR-protection for FPGA technology

Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components

The cost of data dependence in motion vector estimation for reconfigurable platforms

Comparing floating-point and logarithmic number representations for reconfigurable acceleration

Dynamically reconfigurable protocol transducer

Optimal temporal partitioning based on slowdown and retiming

Modeling of glitch effects in FPGA based arithmetic circuits

Design and validation of execution schemes for dynamically reconfigurable architectures

Periodic licensing of FPGA based intellectual property

A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os

A statistical framework for dimensionality reduction implementation in FPGAs

Hardalign: a parallel pairwise alignment hardware application

Decoy circuits for FPGA design protection

Hardware architectures for Monte-Carlo based financial simulations

Customizable FPGA-based architecture for video applications in real time

Super fast hardware string matching

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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