NDLI: Configuration relocation and defragmentation for reconfigurable computing

Content Provider	IEEE Xplore Digital Library
Author	Compton, K. Cooley, J. Knol, S. Hauck, S.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA (Compton, K.)
Abstract	Custom computing systems exhibit significant speedups over traditional microprocessors by mapping compute-intensive sections of a program to reconfigurable logic (Hauck, 1998). However, the high overhead of reconfiguration can limit the execution times achievable with these systems. Research has shown that the ability to relocate and defragment configurations on an FPGA dramatically decreases the overall configuration overhead (Li et al., 2000). We therefore explore the adaptation of the Xilinx 6200 series FPGA for relocation and defragmentation. Due to some of the complexities involved with this structure, we also present a novel architecture designed from the ground up to provide relocation and defragmentation support with a negligible area increase over a generic partially reconfigurable FPGA.
Starting Page	279
Ending Page	280
File Size	215728
Page Count	2
File Format	PDF
ISBN	0769508715
ISSN	10823409
DOI	10.1109/FPGA.2000.903415
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-04-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Routing Circuits Microprocessors Reconfigurable logic Ground support Fabrication Writing
Content Type	Text
Resource Type	Article

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