NDLI: A C to HDL compiler for pipeline processing on FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Maruyama, T. Hoshino, T.
Copyright Year	2000
Description	Author affiliation: Inst. of Eng. Mech. & Syst., Tsukuba Univ., Ibaraki, Japan (Maruyama, T.)
Abstract	In this paper, we show a compiler that generates high speed pipeline circuits for loop and recursive programs written in C programming language, which are the most time exhaustive parts in many application problems. The compiler has following features. First, all operations (except for memory accesses) are divided into cascades of 8-bit width (at maximum) operations in order to achieve high speed clock cycle. Second, in order to fulfil the pipeline, variables that have data feedback dependencies between loop cycles are specially scheduled based on several kinds of optimizing techniques. Furthermore, computations of each loop cycle are speculatively started in every clock cycle even if an array on the same memory bank may be accessed more than once in a loop cycle and there may be data feedback dependencies caused by the array accesses. When the array is accessed more than once, the pipeline is stalled while the array access operations are executed sequentially, and when the feedback dependencies are detected, the speculative computations are cancelled, and restarted after the updates of array are finished. Experiments on simple combinatorial programs showed that the pipeline circuits generated by the compiler run about 39-47 MHz on ALTERA EPF10KA serious (which is as fast as hand optimized circuits), and the speed up by the speculative execution is more than two.
Starting Page	101
Ending Page	110
File Size	825179
Page Count	10
File Format	PDF
ISBN	0769508715
ISSN	10823409
DOI	10.1109/FPGA.2000.903397
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-04-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Pipeline processing Field programmable gate arrays Circuits Program processors Clocks Feedback loop Computer languages Processor scheduling Optimizing compilers
Content Type	Text
Resource Type	Article

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