NDLI: Embedded hardware architectures for scale and rotation invariant feature detection

Content Provider	IEEE Xplore Digital Library
Author	Mishra, P. Nidhi, A. Kishore, J.K. Nandini, S. Iffat, U.
Copyright Year	2014
Description	Author affiliation: Indian Space Res. Organ., Bangalore, India (Kishore, J.K.) \|\| Centre for Intell. Syst., PES Inst. of Technol., Bangalore, India (Mishra, P.; Nidhi, A.; Nandini, S.; Iffat, U.)
Abstract	Scale Invariant Feature Transform is used in many computer vision algorithms like object recognition, motion tracking and stereo matching to name a few. Since the technique is computationally complex, designing low cost embedded architectures to meet real-time constraints is a challenge. To meet this challenge, we propose to use a FPGA-DSP integrated platform. SIFT is divided into two major stages: keypoint detection and descriptor generation. The descriptor generation is implemented using an ARM Cortex based DSP. The more computationally intensive stage of keypoint detection is implemented on the FPGA. In this paper, we present novel, efficient, scalable architectures for the keypoint detection step. The architectures are based on parallelizable and pipelined computational flow. The three designs incorporate a Look Up Table based approach, which makes the use of multipliers obsolete in scale space generation stage. The architectures reduce the time taken for keypoint detection by more than 54%, 91% and 88% respectively as compared to existing designs.
Starting Page	1
Ending Page	6
File Size	3747989
Page Count	6
File Format	PDF
e-ISBN	9781479923175
DOI	10.1109/CONECCT.2014.6740189
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-06
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Scale Invariant Feature Transform Pipelines Dogs Table lookup Field Programmable Gate Arrays Real Time System Indexes Field programmable gate arrays Embedded Computing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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