NDLI: CNTFET full-adders for energy-efficient arithmetic applications

Content Provider	IEEE Xplore Digital Library
Author	Grailoo, M. Hashemi, M. Haghshenas, K. Rezaee, S. Rapolu, S. Nikoubin, T.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran (Hashemi, M.) \|\| Dept. of Electr. & Comput. Eng., Texas Tech Univ., Lubbock, TX, USA (Rapolu, S.; Nikoubin, T.) \|\| Dept. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran (Grailoo, M.; Haghshenas, K.; Rezaee, S.)
Abstract	In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm for CNTFETs, the proposed circuits enjoy full swing in all outputs and internal nodes, structural symmetry, reduced power-delay product (PDP) and energy-delay product (EDP), fairly balanced outputs and high driving capability. The state of the art includes both bulk CMOS and CNTFET technologies. The simulation results exhibit an average PDP and EDP improvement of 9-98% and 55-99% respectively compared with the referenced FAs. All HSPICE simulations were performed on 32nm CNTFET and CMOS process technologies.
Starting Page	1
Ending Page	6
File Size	1248072
Page Count	6
File Format	PDF
e-ISBN	9781479979844
DOI	10.1109/ICCCNT.2015.7395198
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-07-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage fluctuations Fluctuations Full adders Low-power high-speed arithmetic circuits CNTFETs CNT-based pass transistors Adders CMOS-based carbon nanotube Propagation delay
Content Type	Text
Resource Type	Article

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