NDLI: Test wrapper optimization technique using BDF and GA for 3D IP cores

Content Provider	IEEE Xplore Digital Library
Author	Jun Liu Qingqing Qian Xi Wu Ren, F. Wei Wang Tian Chen
Copyright Year	2014
Description	Author affiliation: Dept. of Inf. Sci. & Intell. Syst., Univ. of Tokushima, Tokushima, Japan (Ren, F.) \|\| Sch. of Comput. & Inf., Hefei Univ. of Technol., Hefei, China (Jun Liu; Qingqing Qian; Xi Wu; Wei Wang; Tian Chen)
Abstract	To reduce pre-bond and post-bond test cost for 3D IP (Three Dimensional Intellectual Property) cores, this paper proposed a test wrapper optimization technique using BFD(Best Fit Decreasing) and GA (Genetic Algorithm) algorithm under the constraints of TSVs(Through Silicon Vias) number, the proposed technique firstly used BFD to balance the length of pre-bond wrapper chains to reduce pre-bond test time. Then, on the basis of optimization results of pre-bond wrapper chains, the GA was used to stitch pre-bond wrapper chains to form balanced post-bond wrapper chains under the constrained TSVs number to reduce hardware overhead and post-bond test time. Experimental results demonstrated the presented methodology can effectively reduce hardware overhead at the cost of little increased test time.
Starting Page	1
Ending Page	6
File Size	236608
Page Count	6
File Format	PDF
e-ISBN	9781479926961
DOI	10.1109/ICCCNT.2014.6963012
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-07-11
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware overhead Three-dimensional displays Wrapper chains Sociology Three dimensional intellectual property cores Test time Hardware System-on-chip IP networks Through silicon vias Biological cells Genetic algorithms
Content Type	Text
Resource Type	Article

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