NDLI: An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Saito, H. Yoneda, T. Nakamura, Y.
Copyright Year	2012
Abstract	This paper proposes a multiple task allocationmethod for networks-on-chip (NoC) architecture. The proposedmethod generates two integer linear programming models formultiple task allocation under the total memory size and availableI/O ports. The former model realizes multiple task allocation forNoC nodes to minimize the communication cost. The number ofcopies for each task is given as a constraint. This model is usefulto realize dual or triple execution of tasks for fault tolerance. On the other hand, the latter realizes multiple task allocationfor NoC nodes to maximize the number of executable failurepatterns with the minimization of the communication cost. Anexecutable failure pattern means a combination of failed NoCnodes such that a given application is executed correctly usingsurvived NoC nodes only. This model is useful to maximize faulttolerance even though the memory space is restricted. In theexperiments, for several benchmarks, this paper evaluates theproposed method in terms of the allocation time for both modelsand the number of executable failure patterns for the latter modelwhile changing the size of NoC model.
Starting Page	100
Ending Page	106
File Size	318972
Page Count	7
File Format	PDF
ISBN	9781467325356
e-ISBN	9780769548005
DOI	10.1109/MCSoC.2012.23
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-20
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Fault tolerant systems Minimization Linear programming Resource management
Content Type	Text
Resource Type	Article

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