NDLI: The Design of Host Interface Unit in ARINC659 Bus Control Chip

Content Provider	IEEE Xplore Digital Library
Author	Yu Xiao Xiaoya Fan Jianfeng An
Copyright Year	2012
Abstract	ARINC659 bus control chip is a bus interface chip which supports 4-way redundancy, and a chip which needs to communicate with the processor through PCI9054. This article has made a detailed analysis about local bus timing of the chip PCI9054, designed a host interface unit supporting PCI9054, and programmed the design on FPGA using Verilog HDL language, which accomplishes rapid data read and write and high-speed communication with PCI bus. The program works steadily, has an accurate transmission of data, and can be expanded to other data-transfer system which needs the PCI bus. Currently, the design of this host interface unit has finished the stage of function and timing simulation verification, been able to support PCI9054 to access the internal memory and registers of ARINC659 Bus Control Chip in the combined method of single-cycle and burst, and passed verifying test in FPGA prototype system based on Xilinx.
Starting Page	241
Ending Page	245
File Size	319982
Page Count	5
File Format	PDF
ISBN	9781467306898
e-ISBN	9780769546476
DOI	10.1109/ICCSEE.2012.417
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Simulation verification Host interface unit ARINC659 bus Writing Aerospace electronics PCI9054 Registers Synchronization Hardware design languages Field programmable gate arrays
Content Type	Text
Resource Type	Article

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