NDLI: Low power design flow based on Unified Power Format and Synopsys tool chain

Content Provider	IEEE Xplore Digital Library
Author	Gourisetty, V. Mahmoodi, H. Melikyan, V. Babayan, E. Goldman, R. Holcomb, K. Wood, T.
Copyright Year	2013
Description	Author affiliation: Sch. of Eng., San Francisco State Univ., San Francisco, CA, USA (Gourisetty, V.; Mahmoodi, H.) \|\| Synopsys Inc., Mountain View, CA, USA (Goldman, R.; Holcomb, K.; Wood, T.) \|\| Synopsys Armenia CJSC, Yerevan, Armenia (Melikyan, V.; Babayan, E.)
Abstract	Unified Power Format (UPF) is an industry wide power format specification to implement low power techniques in a design flow. UPF is designed to reflect the power intent of a design at a relatively high level. UPF scripts help describe power intent such as: which power rails to be routed to individual blocks, when blocks are expected to be powered up or shut down, how voltage levels should be shifted between two different power domains, and type of measures taken for retention registers and memory cells contents if the primary power supply to a domain is removed, hence helping the design to be more efficient. With power becoming an important factor in today's electronic systems, there is a need for a more systematic approach to reduce power in complex designs; and UPF is developed to address this need. We have developed the complete UPF based low power design flow from high level behavioral description to physical layout. The design flow is accompanied by an example-driven and self-study tutorial suitable for hands-on teaching. The examples cover a variety of low power methods such as clock-gating, multi-voltage, power gating, and the combination of multi-voltage and power gating. This design flow is implemented using Synopsys electronic design automation tools and tested on Synopsys generic 90nm and 32/28nm libraries. The synthesis scripts are setup in `tcl' format that are compatible with the Synopsys synthesis and physical design tools.
Sponsorship	IEEE Educ. Soc.
Starting Page	28
Ending Page	31
File Size	1629547
Page Count	4
File Format	PDF
ISBN	9781467351133
e-ISBN	9781467351126
DOI	10.1109/IEDEC.2013.6526754
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-03-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Unified Power Format Ground penetrating radar Layout Electronic Design Automation Low Power Logic gates Libraries Standards Clocks
Content Type	Text
Resource Type	Article

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