NDLI: Design of a $4^{th}$ order LP ΣΔ modulator-what about non-idealities?

Content Provider	IEEE Xplore Digital Library
Author	Sandoval-Ibarra, F. Calderon-Preciado, D. Garcia-Sanchez, J.G. Becerra-Alvarez, E.C.
Copyright Year	2014
Description	Author affiliation: Centro Univ. de Cienc. Exactas e Ing., Univ. de Guadalajara, Guadalajara, Mexico (Becerra-Alvarez, E.C.) \|\| Unidad Guadalajara, Cinvestav, Zapopan, Mexico (Sandoval-Ibarra, F.; Calderon-Preciado, D.; Garcia-Sanchez, J.G.)
Abstract	This modulator, a cascade hybrid proposal, takes advantage of both Continuous Time (CT) and Discrete Time (DT) approaches. In order to define a set of specifications Processing Basic-Blocks (PBBs) are firstly analyzed with the help of SIMSIDES. After that transistor-based simulations are carried out not only to verify fulfil specifications, but also to analyse the effect of non-idealities on the modulator performance. The expected response of the modulator is obtained by defining a set of experiments based on analytical models, which allow us to translate all design considerations into a set of values such that the design at transistor level be established according to the desired performance of the proposed architecture. This design strategy perhaps is not the most accurate but it allows us to get a general understanding of the system under design, and also a comprehension at the highest level of abstraction. The system under study is a cascade $4^{th}$ order hybrid Sigma-Delta (ΣΔ) modulator, from which the second stage is a $2^{nd}$ order Low-Pass (LP) DT ΣΔ modulator. The ideal performance of the DT modulator is used to show how non-idealities must be taken into account, and also how to translate design considerations into a set of physical values not only to design PBBs at transistor level, but also to minimize the non-idealities effects up to acceptable values.
Sponsorship	IEEE Argentina Sect.
Starting Page	855
Ending Page	860
File Size	489263
Page Count	6
File Format	PDF
e-ISBN	9781479942695
DOI	10.1109/ARGENCON.2014.6868601
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-11
Publisher Place	Argentina
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Solid modeling Noise Modulation Analog circuits Transistors Mathematical model Integrated circuit modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Behavioral modelling of a $4^{th}$ order LP ΣΔ modulator-towards the design of a hybrid proposal

Non-idealities in analog circuits design: What does it really mean?

Behavior Model of Sigma Delta Modulator for Mobile Digital TV

Modeling of Sigma-Delta Modulator Non-Idealities in MATLAB/SIMULINK

Post-optimization of Delta-Sigma modulators considering circuit non-idealities

Accurate modeling of ultra low-power ΣΔ modulator

Modeling of Sigma-Delta Modulator Non-idealities with Two Step Quantization in MATLAB/SIMULINK

Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching

A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology

Design of a $4^{th}$ order LP ΣΔ modulator-what about non-idealities?

Similar Documents

Behavioral modelling of a $4^{th}$ order LP ΣΔ modulator-towards the design of a hybrid proposal

Non-idealities in analog circuits design: What does it really mean?

Behavior Model of Sigma Delta Modulator for Mobile Digital TV

Modeling of Sigma-Delta Modulator Non-Idealities in MATLAB/SIMULINK

Post-optimization of Delta-Sigma modulators considering circuit non-idealities

Accurate modeling of ultra low-power ΣΔ modulator

Modeling of Sigma-Delta Modulator Non-idealities with Two Step Quantization in MATLAB/SIMULINK

Ensuring correctness of analog circuits in presence of noise and process variations using pattern matching

A 14-bit extended-range incremental ΣΔ ADC matlab-model based on 90nm CMOS-technology

Design of a $4^{th}$ order LP ΣΔ modulator-what about non-idealities?