NDLI: Soft error tolerance using Horizontal-Vertical-Double-Bit Diagonal parity method

Content Provider	IEEE Xplore Digital Library
Author	Rahman, M.S. Sadi, M.S. Ahammed, S. Jurjens, J.
Copyright Year	2015
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Khulna Univ. of Eng. & Technol., Khulna, Bangladesh (Rahman, M.S.; Sadi, M.S.; Ahammed, S.) \|\| Dept. of Comput. Sci., Tech. Univ. Dortmund, Dortmund, Germany (Jurjens, J.)
Abstract	The likelihood of soft errors increase with system complexity, reduction in operational voltages, exponential growth in transistors per chip, increases in clock frequencies and device shrinking. As the memory bit-cell area is condensed, single event upset that would have formerly despoiled only a single bit-cell are now proficient of upsetting multiple contiguous memory bit-cells per particle strike. While these error types are beyond the error handling capabilities of the frequently used error correction codes (ECCs) for single bit, the overhead associated with moving to more sophisticated codes for multi-bit errors is considered to be too costly. To address this issue, this paper presents a new approach to detect and correct multi-bit soft error by using Horizontal-Vertical-Double-Bit-Diagonal (HVDD) parity bits with a comparatively low overhead.
Starting Page	1
Ending Page	6
File Size	1823618
Page Count	6
File Format	PDF
e-ISBN	9781467366762
DOI	10.1109/ICEEICT.2015.7307411
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-21
Publisher Place	Bangladesh
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Soft Error Tolerance Vertical Parity Horizontal Parity Double-Bit Diagonal Parity
Content Type	Text
Resource Type	Article

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