NDLI: Software defined FFT architecture for IEEE 802.11ac

Content Provider	IEEE Xplore Digital Library
Author	Peng Wang McAllister, J. Yun Wu
Copyright Year	2013
Description	Author affiliation: Inst. of Electron., Commun. & Inf. Technol. (ECIT), Queens Univ. Belfast, Belfast, UK (Peng Wang; McAllister, J.; Yun Wu)
Abstract	The upcoming IEEE 802.11ac standard boosts the throughput of previous IEEE 802.11n by adding wider 80 MHz and 160 MHz channels with up to 8 antennas (versus 40 MHz channel and 4 antennas in 802.11n). This necessitates new 1-8 stream 256/512-point Fast Fourier Transform (FFT) / inverse FFT (IFFT) processing with 80/160 MSample/s throughput. Although there are abundant related work, they all fail to meet the requirements of IEEE 802.11ac FFT/IFFT on point size, throughput and multiple data streams at the same time. This paper proposes the first software defined FFT/IFFT architecture as a solution. By making use of a customised soft stream processor on FPGA, we show how a software defined FFT architecture can meet all the requirements of IEEE 802.11ac with low cost and high resource efficiency. When compared with dedicated Xilinx FFT core, our implementation exhibits only one third of the resources also up to three times of resource efficiency.
Starting Page	1246
Ending Page	1249
File Size	1335377
Page Count	4
File Format	PDF
ISBN	9781479902484
DOI	10.1109/GlobalSIP.2013.6737134
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FFT/IFFT Software-defined FPGA 802.11ac Throughput MIMO Real-time systems Soft stream processor Table lookup Resource management Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Soft-core stream processing on FPGA: An FFT case study

FPGA implementation Of FFT processor with OFDM transceiver

Design Space Exploration in an FPGA-Based Software Defined Radio

A FPGA architecture for real-time processing of variable-length FFTS

A high performance four-parallel 128/64-point $radix-2^{4}$ FFT/IFFT processor for MIMO-OFDM systems

Notice of Violation of IEEE Publication PrinciplesEfficient FPGA-mapping of 1024 point FFT Pipeline SDF Processor

Software-Defined Sphere Decoding for FPGA-Based MIMO Detection

FPGA implementation of a CORDIC-based radix-4 FFT processor for real-time harmonic analyzer

Compact CLEFIA Implementation on FPGAS

Software defined FFT architecture for IEEE 802.11ac

Similar Documents

Soft-core stream processing on FPGA: An FFT case study

FPGA implementation Of FFT processor with OFDM transceiver

Design Space Exploration in an FPGA-Based Software Defined Radio

A FPGA architecture for real-time processing of variable-length FFTS

A high performance four-parallel 128/64-point $radix-2^{4}$ FFT/IFFT processor for MIMO-OFDM systems

Notice of Violation of IEEE Publication PrinciplesEfficient FPGA-mapping of 1024 point FFT Pipeline SDF Processor

Software-Defined Sphere Decoding for FPGA-Based MIMO Detection

FPGA implementation of a CORDIC-based radix-4 FFT processor for real-time harmonic analyzer

Compact CLEFIA Implementation on FPGAS

Software defined FFT architecture for IEEE 802.11ac