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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Moussalli, R. Sukhwani, B. Asaad, S. |
| Copyright Year | 2013 |
| Description | Author affiliation: IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA (Moussalli, R.; Sukhwani, B.; Asaad, S.) |
| Abstract | The low latency and high throughput requirements of high-frequency trading has resulted in increasing adoption of dedicated hardware for processing financial feeds. Development of hardware platforms, however, is plagued with slow design/verification cycles compared to their software counterparts. In this work, we present FINPAGE, a FINancial PArser GEnerator, to automatically generate hardware structures for parsing financial feeds. Given a high-level feed format description, FINPAGE generates an area-efficient hardware parser capable of processing feeds at line rate. |
| Starting Page | 1132 |
| Ending Page | 1132 |
| File Size | 224471 |
| Page Count | 1 |
| File Format | |
| ISBN | 9781479902484 |
| DOI | 10.1109/GlobalSIP.2013.6737095 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-03 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer architecture Throughput Hardware Generators Feeds Field programmable gate arrays Payloads |
| Content Type | Text |
| Resource Type | Article |
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