NDLI: Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations

Content Provider	IEEE Xplore Digital Library
Author	Keliris, A. Dimitsas, V. Kremmyda, O. Gizopoulos, D. Maniatakos, M.
Copyright Year	2015
Description	Author affiliation: New York Univ. Abu Dhabi, Abu Dhabi, United Arab Emirates (Maniatakos, M.) \|\| Polytech. Sch. of Eng., New York Univ., New York, NY, USA (Keliris, A.) \|\| Univ. of Athens, Athens, Greece (Dimitsas, V.; Kremmyda, O.; Gizopoulos, D.)
Abstract	As the rate of single-thread CPU performance improvement per generation has diminished due to lower transistor-speed scaling and energy related issues, researchers and industry have shifted their interest towards multi-core and many-core architectures for improving performance. Comparisons between optimized applications for parallel architectures have been quantified many times in the literature, but contradictory results have been reported mainly due to biased methods of evaluating and comparing these architectures. In this paper, we present memory-oblivious optimizations of the widely used Discrete Wavelet Transform (DWT), and provide detailed comparisons of the algorithm on Intel and AMD multi-core CPUs, Nvidia many-core GPUs, as well as the Intel's Xeon Phi many-core coprocessor. Our results indicate that, compared to their respective non-optimized single thread implementations, memory-oblivious optimization delivers up to 17.9×-197.2× performance improvement for the various architectures examined. Furthermore, compared to the state-of-the-art, the presented CPU and GPU memory-oblivious implementations are 2.6× and 1.3× faster respectively than the fastest implementations of DWT currently available in the literature. No comparison to the state-of-the-art can be made for the Xeon Phi, as, to the best of our knowledge, this is the first study that optimizes the DWT for this newfangled architecture.
Starting Page	25
Ending Page	32
File Size	2312401
Page Count	8
File Format	PDF
e-ISBN	9781467394192
DOI	10.1109/PATMOS.2015.7347583
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-01
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image coding Graphics processing units Computer architecture Discrete wavelet transforms Optimization Coprocessors
Content Type	Text
Resource Type	Article

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