NDLI: Enabling energy-aware design decisions for behavioural descriptions containing black-box IP-components

Content Provider	IEEE Xplore Digital Library
Author	Kosmann, L. Lorenz, D. Reimer, A. Nebel, W.
Copyright Year	2013
Description	Author affiliation: OFFIS-Inst. for Inf. Technol., Oldenburg, Germany (Kosmann, L.; Lorenz, D.; Reimer, A.) \|\| Carl von Ossietzky Univ., Oldenburg, Germany (Nebel, W.)
Abstract	The abstraction level of designing digital circuits is rising since high-level synthesis tools are gaining acceptance and are available from different vendors. Simultaneously, the demand for accurate energy estimations on higher abstraction levels is increasing. But estimating energy on these abstraction levels is a difficult task since switching capacitances and area depend on scheduling and allocation decisions which are made during high-level synthesis. In this paper a current energy estimation methodology is extended by a power estimation approach to enable energy-aware design designs on behavioural level. The energy estimation uses control-flow information to model energy and runtime of a component while the power estimation approach generates power and protocol state machines by monitoring external port behaviour and putting it in relation to power dissipation. The methodology is evaluated for a linear predictive coding algorithm receiving its input data from a memory block which is provided as a black-box IP-component. By using the presented estimation methodology, it can be decided at behavioural level whether the usage of this memory element violates a given power budget. The average estimation error for energy is 12.55% while runtime can be estimated with an error of 1.5%.
Starting Page	51
Ending Page	58
File Size	369398
Page Count	8
File Format	PDF
ISBN	9781479911707
DOI	10.1109/PATMOS.2013.6662155
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-09
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Runtime Estimation Switches Logic gates Vectors IP networks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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