NDLI: A Micro Threading Based Concurrency Model for Parallel Computing

Content Provider	IEEE Xplore Digital Library
Author	Qiang Yang Jesshope, C.R. Jian Fu
Copyright Year	2011
Abstract	The continuing launch of various multi-core processors popularizes parallel computing of gaining higher performance, however, it also exerts pressures on software developers concerning how to make full use of the multiplicity of resources to get the required benefits due to high coupling of parallel programs to specified hardware. In this paper, we propose SVP, a micro-threading based concurrency model, as an alternative to efficiently program on and manage multi-core, even many-core systems. SVP isolates programming from executing resources so that programs are compiled once and execute regardless of actual cores available, not only numbers, but also properties to achieve scalable speedup. Such lower coupling, better flexibility and portability in parallel applications are highly appreciated. To investigate SVP, tool chains and a fully functional software simulator of an SVP many-core chip have been developed for test and verification. Using this infra-structure, we are able to show how much we can gain from SVP and how speedup is scaled by running the same binary code of Game of Life on a scalable many-core platform.
Starting Page	1668
Ending Page	1674
File Size	1050336
Page Count	7
File Format	PDF
ISBN	9781612844251
ISSN	15302075
DOI	10.1109/IPDPS.2011.323
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concurrent computing Instruction sets Programming Hardware Synchronization Resource management
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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