NDLI: Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture

Content Provider	IEEE Xplore Digital Library
Author	Keceli, F. Tzannes, A. Caragea, G.C. Barua, R. Vishkin, U.
Copyright Year	2011
Abstract	The Explicit Multi-Threading (XMT) is a general-purpose many-core computing platform, with the vision of a 1000-core chip that is easy to program but does not compromise on performance. This paper presents a publicly available tool chain for XMT, complete with a highly configurable cycle-accurate simulator and an optimizing compiler. The XMT tool chain has matured and has been validated to a point where its description merits publication. In particular, research and experimentation enabled by the tool chain played a central role in supporting the ease-of-programming and performance aspects of the XMT architecture. The compiler and the simulator are also important milestones for an efficient programmer's workflow from PRAM algorithms to programs that run on the shared memory XMT hardware. This workflow is a key component in accomplishing the dual goal of ease-of-programming and performance. The applicability of our tool chain extends beyond specific XMT choices. It can be used to explore the much greater design space of shared memory many-cores by system researchers or by programmers. As the tool chain can practically run on any computer, it provides a supportive environment for teaching parallel algorithmic thinking with a programming component. Unobstructed by techniques such as decomposition-first and programming for locality, this environment may be useful in deferring the teaching of these techniques, when desired, to more advanced or platform-specific courses.
Starting Page	1282
Ending Page	1291
File Size	754864
Page Count	10
File Format	PDF
ISBN	9781612844251
ISSN	15302075
DOI	10.1109/IPDPS.2011.270
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Program processors Computer architecture Parallel processing Programming Phase change random access memory Assembly
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

R.: Toolchain for programming, simulating and studying the XMT many-core architecture

Toolchain for programming, simulating and studying the xmt many-core architecture (2011)

Toolchain for programming, simulating and studying the xmt many-core architecture (2011)

The design and analysis of parallel algorithms

XMT-GPU: A PRAM Architecture for Graphics Computation

Writing sequential programs for parallel processors: implementation experience

Simple parallel biconnectivity algorithms for multicore platforms

Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures

A PRAM-on-chip vision

Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture

Similar Documents

R.: Toolchain for programming, simulating and studying the XMT many-core architecture

Toolchain for programming, simulating and studying the xmt many-core architecture (2011)

Toolchain for programming, simulating and studying the xmt many-core architecture (2011)

The design and analysis of parallel algorithms

XMT-GPU: A PRAM Architecture for Graphics Computation

Writing sequential programs for parallel processors: implementation experience

Simple parallel biconnectivity algorithms for multicore platforms

Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures

A PRAM-on-chip vision

Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture