NDLI: FPGA-based embedded system implementation of finger vein biometrics

Content Provider	IEEE Xplore Digital Library
Author	Khalil-Hani, M. Eng, P.C.
Copyright Year	2010
Description	Author affiliation: VLSI-eCAD Research Laboratory (VeCAD), Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Johor, Malaysia (Khalil-Hani, M.; Eng, P.C.)
Abstract	With the ubiquitous deployment and rapid growth of electronic information systems in today's society, personal or identity verification is now a critical key problem. Due to this fact, biometric authentication has emergently gaining popularity as it provides a high security and reliable approach for personal authentication. However, authentication using ones biometric features has not been widely implemented in a real time embedded system. Thus, in this paper, a novel approach to personal verification using infrared finger vein biometric authentication implemented on FPGA-based embedded system is presented. Creating a biometric authentication system in this resource-constrained embedded system for a real-time application, being a challenging problem in itself, is a significant contribution of this work. The proposed biometric system consists of four modules, namely image acquisition, image pre-processing, feature extraction, and matching. Feature extraction is based on minutiae extracted from the vein pattern image, while the biometric matching utilizes a technique based on the Modified Hausdorff Distance. The system is prototyped on Altera Stratix II FPGA hardware board with Nios2-Linux Real Time Operating System running at 100MHz clock rate. Experiments conducted on a database of 100 images from 20 different hands shows encouraging results with system acceptable accuracy of less than 1.004%. Our first version of the embedded system, which is wholly in firmware, resulted in an execution time of $1953×10^{6}$ clock cycles or 19 seconds. The results demonstrate that our approach is valid and effective for vein-pattern biometric authentication.
Starting Page	700
Ending Page	705
File Size	598259
Page Count	6
File Format	PDF
ISBN	9781424476459
e-ISBN	9781424476473
DOI	10.1109/ISIEA.2010.5679376
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-03
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Biometrics RTOS Embedded System Biometric Veins Fingers FPGA Authentication Gray-scale Feature extraction Finger Vein Pixel
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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