NDLI: Analysis of CMOS differential input to increase ICMR of folded cascode operational amplifier

Content Provider	IEEE Xplore Digital Library
Author	Fuad, W.I.W. Ali, A.H.
Copyright Year	2010
Description	Author affiliation: University Kuala Lumpur British Malaysian Institute (Fuad, W.I.W.; Ali, A.H.)
Abstract	This paper presents a CMOS latched comparator designed for low power analog to digital conversion application. The circuit consists of a rail-to-rail operational transconductance amplifier followed by a dynamic latch to achieve a fast, high resolution performance at low power. The regenerative latch efficiently reduces the number of gain stage needed and consumes negligibly small static power. The amplifier acts as a preamplifier providing sufficient gain to overcome dynamic offset of dynamic latch. Simulation across process and temperature variation shows the circuit has reliable operation as low as 2.7V in a standard CMOS 0.18μm mixed signal process. The circuit consumes maximum of 111μA typical current. Average delay is 2.25ns and easily operates at 10MHz.
Starting Page	711
Ending Page	715
File Size	370031
Page Count	5
File Format	PDF
ISBN	9781424476459
e-ISBN	9781424476473
DOI	10.1109/ISIEA.2010.5679374
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-03
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Rail to Rail Latches Folded Cascode Low Power Preamplifiers CMOS integrated circuits Topology Transistors Integrated circuit modeling Latched Comparator
Content Type	Text
Resource Type	Article

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