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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kohama, K. Ohgihara, T. Murakami, Y. |
| Copyright Year | 1995 |
| Description | Author affiliation: Semicond. Co., Sony Corp., Kanagawa, Japan (Kohama, K.; Ohgihara, T.; Murakami, Y.) |
| Abstract | In this paper, we propose two types of new DPDT switch GaAs JFET MMICs for digital cellular handsets. These ICs have excellent performances of low insertion loss and high power handling capability even with a low control voltage by stacking three JFETs with shallow Vp and using a novel bias circuit. One DPDT switch IC has two shunt FET blocks and can obtain high isolation without external parts. Insertion loss smaller than 0.6 dB and isolation over 25 dB up to 2 GHz were achieved. P1 dB was about 35 dBm even with the control voltage of 0/3 V. Another DPDT switch IC utilizes a parallel resonance of external inductor and parasitic capacitance between drain and source of OFF state FETs. By attaching 15 nH inductors, for example, the IC exhibited insertion loss as low as 0.4 dB and isolation of better than 40 dB at 1.5 GHz, and P1 dB was about 34 dBm with the 0/3 V control. |
| Starting Page | 75 |
| Ending Page | 78 |
| File Size | 507965 |
| Page Count | 4 |
| File Format | |
| ISBN | 078032966X |
| DOI | 10.1109/GAAS.1995.528965 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-10-29 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Low voltage Gallium arsenide Stacking Switches Insertion loss MMICs Telephone sets Voltage control Inductors FETs |
| Content Type | Text |
| Resource Type | Article |
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