NDLI: FPGA-based system for data acquisition and remote communication

Content Provider	IEEE Xplore Digital Library
Author	Mazare, A. Ionescu, L. Serban, G. Lita, I.
Copyright Year	2014
Description	Author affiliation: Fac. of Electron., Commun. & Comput., Univ. of Pitesti, Pitesti, Romania (Mazare, A.; Ionescu, L.; Serban, G.; Lita, I.)
Abstract	In this paper we present a system that we made for acquisition and processing of data on multiple channels (8 in total) and transmitting the remote results through the Ethernet interface. The solution chosen by us involves the system implementing in FPGA where any processes running in parallel can be described - the acquisition processes from the AD sensors and possibly data processing processes. Our solution is a fully integrated system in an FPGA, which is composed of two main parts: the acquisition and processing of data part, made of modules (IP core) working in parallel and the communication part that consists of an architect of RISC processor, which takes the data processed by the parallel modules and can transmit them by running libraries for the TCPIP communication, just like a stand-alone processor. The solution was basically made on a Xilinx Spartan 6 FPGA circuit to which eight AD converters are connected, each taking data from one sensor. The model has an Ethernet interface which was used for remote data communication. On the processor implemented by us in FPGA we ran a TCP server, which through a client-server session allows the communication of the data.
Starting Page	169
Ending Page	174
File Size	320184
Page Count	6
File Format	PDF
ISBN	9781479969623
DOI	10.1109/SIITME.2014.6967019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-23
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing FPGA Ports (Computers) Multi-channel acquisition system Computer architecture Ethernet Sensors Registers IP networks Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

The Data Transmission System Design between Intelligent Multi-serial Port and Ethernet Based on ARM and FPGA

SoC platform design with multi-channel bus architecture

Design of the Multi-channel Ultrasonic Signal Acquisition and Denoising Based on FPGA

A general xTCA compliant and FPGA based data processing building blocks for trigger and data acquisition system

Time optimization of instruction execution in FPGA using embedded systems

The solution of ethernet based on hardware protocol stack W5300 and FPGA

Design of FPGA based 8-bit RISC controller IP core using VHDL

Efficient PC-FPGA Communication over Gigabit Ethernet

Acquisition board design of high-speed image data based on ARM and FPGA

FPGA-based system for data acquisition and remote communication

Similar Documents

The Data Transmission System Design between Intelligent Multi-serial Port and Ethernet Based on ARM and FPGA

SoC platform design with multi-channel bus architecture

Design of the Multi-channel Ultrasonic Signal Acquisition and Denoising Based on FPGA

A general xTCA compliant and FPGA based data processing building blocks for trigger and data acquisition system

Time optimization of instruction execution in FPGA using embedded systems

The solution of ethernet based on hardware protocol stack W5300 and FPGA

Design of FPGA based 8-bit RISC controller IP core using VHDL

Efficient PC-FPGA Communication over Gigabit Ethernet

Acquisition board design of high-speed image data based on ARM and FPGA

FPGA-based system for data acquisition and remote communication