NDLI: Processor power simulator for low power code generation using look up table

Content Provider	IEEE Xplore Digital Library
Author	Hun-ho Ham Chan-oh Park Jong-hak Kim Jueng-hun Kim Jun-dong Cho
Copyright Year	2011
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Sungkyunkwan Univ., Suwon, South Korea (Hun-ho Ham; Chan-oh Park; Jong-hak Kim; Jueng-hun Kim; Jun-dong Cho)
Abstract	In this paper, we propose a software-level power simulator that measures power consumption for each instruction of RTL processor and builds on a LUT so as to attain low power code generation. Recently, as demands for mobile device with new concept, such as smart phone and tablet PC, have been increasing rapidly, development of low power embedded processor is mandatory. Since these devices usually consist of complex software system for multiple functions, accomplishment of low power technology by optimizing software algorithms has been magnified. In optimizing software algorithms, the most essential part is low power source coding maintaining the required speed. In this paper, we propose a highly adaptable power simulator for a certain given processor using register transfer level code. Our suggested power simulator could easily identify the power consumption of different source codes that have the same function so as to obtain reference data to optimize software algorithms for low power design. In our experiments, applying our power simulator to the number of source codes before and after optimization, we could obtain a low power source code with on the average of 29.9% reduction in power consumption.
Sponsorship	IEEE
Starting Page	550
Ending Page	553
File Size	230350
Page Count	4
File Format	PDF
ISBN	9781457704727
e-ISBN	9788988678558
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-29
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	AICIT
Subject Keyword	Power Simulator Power measurement Code optimization Low power Embedded process
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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