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A CAM Emulator Using Look-Up Table Cascades (2007)
| Content Provider | CiteSeerX |
|---|---|
| Author | Nakahara, Hiroki Sasao, Tsutomu Matsuura, Munehiro |
| Description | An address table relates k different registered vectors to the addresses from 1 to k. An address generation function represents the address table. This paper presents a realization of an address generation function with an LUT cascade on an FPGA. The address generation function is implemented by BRAMs of an FPGA, while the addition and the deletion of registered vectors are implemented by an embedded processor on the FPGA. Compared with CAMs produced by the Xilinx Core Generator, our implementations are smaller and faster. This paper also shows that the addition and deletion of a registered vector can be done in time that is proportional to the number of cells in the LUT cascade. |
| File Format | |
| Language | English |
| Publisher Date | 2007-01-01 |
| Publisher Institution | 14TH RECONFIGURABLE ARCHITECTURES WORKSHOP RAW 2007, MARCH 2007, LONG BEACH CALIFORNIA, USA |
| Access Restriction | Open |
| Subject Keyword | Address Generation Function Embedded Processor Lut Cascade Xilinx Core Generator Registered Vector Address Table |
| Content Type | Text |
| Resource Type | Article |
