NDLI: Implementation of simple SNORT processor for efficient Intrusion Detection systems

Content Provider	IEEE Xplore Digital Library
Author	Azimi, E. Ghaznavi-Ghoushchi, M.B. Rahmani, A.M.
Copyright Year	2009
Description	Author affiliation: Dept. of EE. School of Engineering, Shahed University, Tehran, Iran (Ghaznavi-Ghoushchi, M.B.) \|\| Dept. of CE. School of Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran (Azimi, E.; Rahmani, A.M.)
Abstract	In this paper, a method is proposed for hardware implementation of basic instructions of SNORT software for using in hardware accelerator systems relating to Network Intrusion Detection (NID). The design is implemented in Verilog hardware description language. The design is synthesized both in FPGA on Virtex5 and ASIC (with CMOS Technology 90nm and 65nm). Initial results of hardware description simulation agree with those of SNORT. Similarity between these two results shows that the proposed hardware infrastructure can be exploited as a hardware accelerator in different applications of Intrusion Detection (ID) within networks where needs high processing rate for multi Gb/s data rates. The ASIC synthesis results indicate that the proposed hardware can process payload section of a TCP/IP stream with the rate of 1 Gb/s and 2 Gb/s in TSMC 90nm and TSMC 65nm respectively.
Starting Page	533
Ending Page	537
File Size	163407
Page Count	5
File Format	PDF
ISBN	9781424447541
DOI	10.1109/ICICISYS.2009.5358130
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FPGA Hardware description languges Open source software Application specific integrated circuits ASIC Network intrusion detection systems Snort Operating systems Intrusion detection Hardware accelerators Software systems Computer networks Network synthesis Hardware design languages Pattern matching Field programmable gate arrays
Content Type	Text
Resource Type	Article

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