NDLI: Using FPGAs to Supplement Ray-Tracing Computations on the Cray XD-1

Content Provider	IEEE Xplore Digital Library
Author	Cameron, C.B.
Copyright Year	2007
Description	Author affiliation: US Naval Acad., Annapolis (Cameron, C.B.)
Abstract	Optical ray tracing simulations in lens design commonly employ six major computations: the point of intersection of a ray and an optical surface, a check to see whether the ray is inside a restrictive aperture, calculation of a unit vector normal to the surface at the point of intersection, the result of reflection or refraction of the ray at the surface, and coordinate conversions of the new ray's starting position and direction to facilitate repetition of the calculations at succeeding optical elements. Because the rays are independent of one another, ray tracing can benefit greatly from parallel processing, especially when there are billions of rays to be traced. The efficiency of using 839 AMD Opteron processors for this application has been shown to be 97.9 %. This means that adding additional processors is a highly effective strategy for increasing the rate of ray tracing, thus reducing the time of simulation. Using field-programmable gate arrays (FPGA) is an effective strategy for further increasing the rate of ray tracing. In this paper we describe key aspects of implementing deeply pipelined processors within an FPGA to perform scientific computations, using them to supplement the ray tracing provided by the sequential Opteron processors in the Cray XD-1. The discussion includes how to schedule the use of the FPGA's internal resources, synchronize the interaction between the FPGA and the Opterons, and assess the fraction of time that each major computational resource within the FPGA is in use. We discuss a method that guarantees 100 % efficiency of the critical resource, the resource needed most often for a specific computation. We also consider how to increase the efficiency of the non-critical computational resources within the FPGA and what the side effects of such changes can be.
Starting Page	359
Ending Page	363
File Size	133844
Page Count	5
File Format	PDF
ISBN	9780769530885
DOI	10.1109/HPCMP-UGC.2007.79
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optical design Computational modeling Optical computing Ray tracing Apertures Parallel processing Optical refraction Optical reflection Field programmable gate arrays Lenses
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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