NDLI: Digital Circuit Design Using Support Vector Machines

Content Provider	IEEE Xplore Digital Library
Author	Manikandan, J. Agrawal, V.K.
Copyright Year	2014
Description	Author affiliation: Crucible of Res. &Innovation, PES Inst. of Technol., Bangalore, India (Manikandan, J.; Agrawal, V.K.)
Abstract	Digital circuits are preferred over its analog counterpart with the invention of microprocessors, microcontrollers, digital signal processors and Field Programmable Gate Arrays (FPGA). Digital circuits in the form of digital arithmetic and digital logics are employed for various applications. On the other side, Support Vector Machine (SVM) is considered as a state-of-the-art tool for pattern recognition. In this paper, a novel attempt is made to study, assess and design digital circuits using two-class and multi class support vector machine classifiers. It is reported in literature that computational complexity and the classification time for SVM classifier depends on the number of support vectors required for classification. In order to reduce the number of support vectors, an optimum threshold technique based SVM classifier is employed for the design of digital circuits and it is observed that a maximum of 87.5% of total support vectors are pruned on using the technique.
Sponsorship	IEEE Comput. Soc.
Starting Page	1114
Ending Page	1118
File Size	1112119
Page Count	5
File Format	PDF
e-ISBN	9781479930708
DOI	10.1109/CSNT.2014.228
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Support vector machines Multiplexing Pattern Classification Accuracy Logic gates Decoding Support Vector Machines Machine Learning Digital circuits Adders
Content Type	Text
Resource Type	Article

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