NDLI: Design of downlink PDSCH architecture for LTE using FPGA

Content Provider	IEEE Xplore Digital Library
Author	Abbas, S.S.A. Sheeba, P.A.J. Thiruvengadam, S.J.
Copyright Year	2011
Description	Author affiliation: Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivaksi-626005, India (Abbas, S.S.A.; Sheeba, P.A.J.) \|\| Thiagarajar College of Engineering, Madurai - 625015, India (Thiruvengadam, S.J.)
Abstract	The LTE specification provides a framework for increased capacity, improved spectrum efficiency, improved coverage, reduced cost per bit for the operator, and reduced latency compared with previous wireless implementations. The 3GPP LTE system should support instantaneous downlink and uplink peak data rates of 100Mb/s and 50Mb/s within 20 MHz downlink and uplink spectrum allocations, respectively. LTE allows operators to provide different services based on spectrum. LTE improves spectral efficiency in 3G networks. This paper focuses on the transmitter architecture of the downlink data channel PDSCH comprising Scrambling, Modulation, Layer Mapping, Precoding, addition of parity bits to precoded output and mapping to resource elements and receiver architecture comprising Demapping from Resource Elements, Removal of parity bits, Decoding, Delayer Mapping, Demodulation and Descrambling as described in the LTE specifications.
Starting Page	947
Ending Page	952
File Size	321129
Page Count	6
File Format	PDF
ISBN	9781457705885
e-ISBN	9781457705908
DOI	10.1109/ICRTIT.2011.5972424
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	PDSCH Layer Mapping Transmitting antennas Modulation Receivers Computer architecture Mapping to Resource Element Downlink Scrambling LTE Preceding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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