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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mehrizi, H.S. Zeinali, E. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electr., IT & Comput. Sci., Islamic Azad Univ., Qazvin, Iran (Mehrizi, H.S.; Zeinali, E.) |
| Abstract | This paper presents an adaptive routing algorithm for 2D mesh network-on-chips (NoCs). The algorithm is based on DyXY routing algorithm. Our proposed routing algorithm is a very low cost fault-tolerance routing method to tolerate at least one faulty link in mesh-based on chip networks. It is a distributed, adaptive, congestion-aware and deadlock-free routing algorithm where only two virtual channels are used for adaptiveness and fault-tolerance. This is obtained by using two congestion flags between each two nodes which demonstrate the existence of congestion in a row or column. The same flags may be used to alarm a link failure in a row or column. The network performance, fault-tolerance capability and hardware overhead are computed through appropriate simulations. The experimental results show that the overall reliability and throughput of a NoCs is significantly elevated against at least one link failure with only a small latency overhead. |
| Sponsorship | IEEE Poland Sect. CAS Chapt. |
| Starting Page | 354 |
| Ending Page | 359 |
| File Size | 973986 |
| Page Count | 6 |
| File Format | |
| ISBN | 9788362065172 |
| ISSN | 23260319 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-09-26 |
| Publisher Place | Poland |
| Access Restriction | Subscribed |
| Rights Holder | Poznan Univ of Technology |
| Subject Keyword | Performance evaluation Virtual channel Fault tolerance Routing algorithm Fault tolerant systems Network-on-chip Routing Congestion Reconfiguration |
| Content Type | Text |
| Resource Type | Article |
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