NDLI: Design of low power fault tolerant reversible multiplexer using QCA

Content Provider	IEEE Xplore Digital Library
Author	Maity, M. Ghosal, P. Das, B.
Copyright Year	2012
Description	Author affiliation: West Bengal University of Technology, India (Das, B.) \|\| Bengal Engineering and Science University, Shibpur, India (Maity, M.; Ghosal, P.)
Abstract	Reversible logic has emerged as a promising computing paradigm having its applications in low power CMOS design, quantum computing and nanotechnology in recent years. In this paper a fault tolerant reversible multiplexer (MUX) has been proposed using a parity preserving Fredkin gate for the first time. Proposed 2:1 MUX has been designed using only one Fredkin gate which has produced two garbage outputs. The proposed parity preserving reversible multiplexer circuit is more efficient in power dissipation and fault tolerance. It should be a promising step towards the low power, nano-scale circuit design for the future generation quantum computer.
Starting Page	467
Ending Page	470
File Size	858778
Page Count	4
File Format	PDF
ISBN	9781467318280
e-ISBN	9781467318273
DOI	10.1109/EAIT.2012.6408019
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-30
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Fault tolerance Fault tolerant systems Energy dissipation Low power computing Logic gates Vectors Reversible multiplexer QCA Fault tolerant reversible computing Clocks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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