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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Keerthana, K. Shanmugaraja, M. MaheshKannan, P. |
| Copyright Year | 2015 |
| Description | Author affiliation: Karpaga Vinayaga Coll. of Eng. & Technol., Chennai, India (Keerthana, K.; Shanmugaraja, M.) || Dept. of ECE, Pondicherry Eng. Coll., Pondicherry, India (MaheshKannan, P.) |
| Abstract | The objective is to design and simulate the high speed low power pulse triggered flip-flop and to reduce the dynamic power consumption of the flip flop by applying pulse triggering method used for the clocks. Since the on time of the clock pulses are narrowed down, the dynamic power dissipation of the flip flop is greatly reduced. Here, a dedicated pulse generation circuit is used to provide clock pulse with very short on time so that the flip flop switching time is reduced to achieve reduction in the dynamic power dissipation. The design is implemented in GPDK 90nm technology using Cadence Virtuoso Schematic Composer and the Spectre as the simulator. |
| Starting Page | 0392 |
| Ending Page | 0397 |
| File Size | 1016864 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781479980819 |
| DOI | 10.1109/ICCSP.2015.7322915 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-04-02 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | High Speed Pulse Triggered Low Power Signal Feed Through |
| Content Type | Text |
| Resource Type | Article |
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