Loading...
Please wait, while we are loading the content...
Similar Documents
Enhancement of Low Power Pulse Triggered Flip-Flop Design Based on Signal Feed-Through Scheme using Pulse-Enhance
| Content Provider | Semantic Scholar |
|---|---|
| Author | Sriramasarma, Banda. Babu, P. Bujji |
| Copyright Year | 2014 |
| Abstract | Low Power research major concern in today’s VLSI word. Practically, clocking system like flip-flop (FF) consumes large portion of total chip power. So in this paper we discuss about the design of the clock system using novel Flip-Flop design. In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. Pulsetriggered FF (P-FF) has been considered as a popular alternative to the conventional master – slave based F. a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulsetriggered FF (P-FF) designs and achieves better speed and power performance in the applications of high speed. These circuits are simulated using Tanner Tools with TSMC018 technology. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://ijarf.com/wp-content/uploads/2014/12/IJEEE-7-9-Enhancement-of-Low-Power-Pulse-Triggered-Flip-Flop-Design-Based-on-Signal-Feed-Through-Scheme-using-Pulse-Enhance.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
